Multiplexer with level shift capabilities

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding

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Details

326 68, 326 81, 327410, H03K 19084, H03K 19094

Patent

active

055347983

ABSTRACT:
An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.

REFERENCES:
patent: 3621288 (1971-11-01), Brown
patent: 4038564 (1977-07-01), Hakata
patent: 4975597 (1990-12-01), Houston
patent: 5012126 (1991-04-01), Feldbaumer et al.
patent: 5416367 (1995-05-01), Chan et al.

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