Testing scheme that re-uses original stimulus for testing circui

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327202, G01R 3128

Patent

active

057744750

ABSTRACT:
A testing circuit for use in testing X number of portions of circuitry embedded within a larger circuit. The testing circuit includes Y number of scan flip-flops which each have a normal data input, a scan data input, a data select input, a clock input and a data output. The scan flip-flops are serially coupled together such that the scan data input of a first flip-flop forms a serial data input for the testing circuit, the data output of a last flip-flop forms a serial data output for the testing circuit, the scan data input of each remaining flip-flop is connected to the data output of a previous flip-flop, the normal data input of at least one of the scan flip-flops forms an unload bus, and the data select signal of at least one of the scan flip-flops forms a test enable signal which enables one of the serial data input and the unload bus. Also included are Y number of latches which each have a data input, a clock input and a data output. Each of the latches has its data input and its clock input connected to the data output and the data select input, respectively, of a different one of the scan flip-flops. The data output of at least one of the latches forms a load bus. A set of X number of input multiplexers each have an input coupled to the load bus and an output coupled to a different one of the X number of portions of circuitry. An output multiplexer has an output and X number of inputs. The output is coupled to the unload bus and each of the inputs are coupled to a different one of the X number of portions of circuitry.

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