Error correction apparatus

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

371 3711, H03M 1300, G06F 7552

Patent

active

057743894

ABSTRACT:
An error correction apparatus is disclosed for use in erasure correction and error correction in transmission paths of devices such as optical disk devices, upon receipt of input data of various formats. The apparatus has a select signal generating circuit for generating, in response to the format of the input data, a select signal corresponding to the format of the input data. Also taught is an erasure correction and error correction circuit for conducting error correction which includes erasure correction; and a controlling circuit for controlling the erasure correction and error correction in accordance with the select signal so as to conduct correction in conformity with the format of the input data. Thus, erasure correction and error correction can be conducted, regardless of format of the input data.

REFERENCES:
patent: 4151510 (1979-04-01), Howell et al.
patent: 4162480 (1979-07-01), Berlekamp
patent: 4216531 (1980-08-01), Chiu
patent: 4218582 (1980-08-01), Hellman et al.
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4476562 (1984-10-01), Sako et al.
patent: 4498178 (1985-02-01), Ohhashi
patent: 4567600 (1986-01-01), Massey et al.
patent: 4649541 (1987-03-01), Lahmeyer
patent: 4658094 (1987-04-01), Clark
patent: 4675869 (1987-06-01), Driessen
patent: 4759063 (1988-07-01), Chaum
patent: 4797848 (1989-01-01), Walby
Arai, et al., Digital Signal Processing Technology for R-DAT, IEEE Transactions on Consumer Electronics, vol. CE-32, No. 3, Aug. 1986, pp. 740-749.
Tanaka, et al., Application of Generalized Product Code for Stationary-Head Type Professional Digital Audio Recorder, The Transactions of the IECE of Japan, vol. E 69, No. 6, Jun. 1986, pp. 416-423.
Hsu, et al., The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm, IEEE Transactions on Computers, vol. C-33, No. 10, Oct. 1984, pp. 906-911.
Japanese Patent Abstract vol. 7, No. 238 for Kokai No. 58-125175, Jul. 1983.
Wang, et al., VLSI Architectures for Computing Multiplicatons and Inverses in GF(2.sup.m), 8092 IEEE Transactions on Computers, pp. 709-717, Aug. 1985.
Scott, et al., A Fast VLSI Multiplier for GF(2.sup.m), 8272 IEEE Journal on Selected Areas in Communications SAC-4, pp. 62-66, Jan. 1986.
NASA Tech Brief, Multiplier Architecture for Coding Circuits, 2301 N.T.I.S. Technical Notes, No. 7, p. 1, Jul. 1986.
Redinbo, Fault-Tolerant Digital Filtering Structures for Wafer Scale VLSI, pp. 1189-1192, 1986.
Lin, et al., Error Control Coding, Prentice-Hall, Inc., 1983, pp. 161-167.
Patent Abstracts of Japan, Kokai 58-219851, vol. 8, No. 70, Dec. 1983.
Maki, et al., A VLSI Reed Solomon Encoder: An Engineering Approach, IEEE Custom Integrated Circuits Conference, May 1986, pp. 177-181.
Glover, et al., Practical Error Correction Design for Engineers, 1st Ed., pub. 1982 by Data Systems Technology Corp., pp. 105-118.
Glover, et al., Practical Error Correction Design for Engineers, 2nd Ed., pub. 1982 by Data Systems Technology Corp., p. 106.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Error correction apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error correction apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction apparatus will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1867078

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.