Delayed interrupts with a FIFO in an improved input/output archi

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395868, G06F 946

Patent

active

057548668

ABSTRACT:
Apparatus for transferring commands over a system transmission path between first and second components in a digital data system including a first-in first-out circuit having a plurality of stages arranged in the system transmission path, circuitry for generating a first signal to indicate that a component to which a command in the FIFO circuit is directed is unable to handle an operation commanded, and a delay circuit responsive to the first signal for causing the generation of an interrupt request signal after a preselected time.

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