Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1995-09-22
1998-05-19
Wallace, Valencia Martin
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257315, 257317, 257318, 438264, 3651851, 3651856, H01L 29788
Patent
active
057539529
ABSTRACT:
An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages V.sub.T, and improves device life because fewer electrons travel through the gate oxide (30).
REFERENCES:
patent: 5412603 (1995-05-01), Schreck et al.
patent: 5554552 (1996-09-01), Chi
Kurylo et al., "Nonvolatile MIS Charge Storage Devices", IBM Technical Disclosure bulletin, vol. 19, No. 3, pp. 871-872, Aug. 1976.
Donaldson Richard L.
Holland Robby T.
Lindgren Theodore D.
Martin Wallace Valencia
Texas Instruments Incorporated
LandOfFree
Nonvolatile memory cell with P-N junction formed in polysilicon does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile memory cell with P-N junction formed in polysilicon , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory cell with P-N junction formed in polysilicon will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1855498