Serial access memory capable of reading data serially at a speed

Static information storage and retrieval – Read/write circuit

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365221, 365233, G11C 700

Patent

active

052650499

ABSTRACT:
A serial access memory capable of reading out data serially at a speed double the writing speed. The memory is implemented as a semiconductor chip having an edge detecting circuit and a clock doubling circuit for data read-out mounted thereon. The edge detecting circuit detects the positive-going and negative-going edges of a clock fed to the chip from the outside. In response to the output of the edge detecting circuit, the clock doubling circuit generates a read clock having a frequency double the frequency of the external clock. The double-speed clock generated within the chip reduces the cost of the memory.

REFERENCES:
patent: 4710966 (1987-12-01), Aufiero
patent: 4755971 (1988-07-01), Jasmer et al.
patent: 4815036 (1989-03-01), Kyomasu
patent: 4823321 (1989-04-01), Aoyama
patent: 4945518 (1990-07-01), Muramatsu et al.
patent: 5018110 (1991-05-01), Sugiyama et al.

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