Floating bitline test mode with digitally controllable bitline e

Details Floating bitline test mode with digitally controllable bitline e Floating bitline test mode with digitally controllable bitline e

1997-09-25

1998-12-08

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 365210, 36518509, G11C 700

Patent

active

058480080

ABSTRACT:
A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.

REFERENCES:
patent: 4654827 (1987-03-01), Childers
patent: 4868823 (1989-09-01), White, Jr. et al.
patent: 5532963 (1996-07-01), Kushiyama et al.
patent: 5574729 (1996-11-01), Kinoshita et al.
patent: 5619460 (1997-04-01), Kirihata et al.
patent: 5680354 (1997-10-01), Kawagoe
patent: 5748545 (1998-05-01), Lee et al.

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