Method of calculating a parasitic load in a semiconductor integr

Details Method of calculating a parasitic load in a semiconductor integr Method of calculating a parasitic load in a semiconductor integr

1996-07-31

1998-12-08

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364491, 364578, 395500, G06F 1700

Patent

active

058479678

ABSTRACT:
A reference connection pattern is determined within a three-dimensional region together with the other connection patterns to extract data for pattern matching operation from a position of each connection pattern. An estimated parasitic load is also given as the data and is stored as a part of reference pattern data to form a data base. By the pattern matching operation between the reference pattern data and an object pattern, a coincident one of the reference pattern data is determined as a practical parasitic load. Thus, the estimated parasitic load included in the reference pattern data is detected as the practical parasitic load in the object pattern.

REFERENCES:
patent: 4651284 (1987-03-01), Watanabe et al.
patent: 5086477 (1992-02-01), Yu et al.
patent: 5452224 (1995-09-01), Smith, Jr. et al.

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