Latching ECL to CMOS input buffer circuit

Details Latching ECL to CMOS input buffer circuit Latching ECL to CMOS input buffer circuit

1994-05-23

1995-06-20

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326 73, 327215, 36518911, H03K 1901

Patent

active

054263816

ABSTRACT:
A latching ECL to CMOS input buffer (20) has an input buffer (21) for receiving an ECL input signal, a CMOS latch (35), and driver circuits (55, 65). Transmission gates (31, 32) are used to couple the input buffer (21) to the latch (35) in response to a CMOS clock signal being a logic low. The driver circuits (55, 65) are coupled to transmission gates (31, 32). While the clock signal is a logic low, input nodes of the first and second driver circuits (55, 65) are precharged to a relatively high voltage in order to isolate the input signal from the first and second driver circuits (55, 65). The latch (35) both latches the logic state of the ECL input signal and converts the ECL input signal to CMOS logic levels. This allows an input signal to be latched and level converted within a relatively short period of time.

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