Phase-locking method and a loop applying the method

Details Phase-locking method and a loop applying the method Phase-locking method and a loop applying the method

1996-05-30

1997-11-04

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 17, H03D 324

Patent

active

056848447

ABSTRACT:
The relates to locking the phase of output signal (Ys) relative to an input signal (Ye). A first frequency correction signal (Yr1) is obtained by integrating a signal representative of an error of said phase relative to a reference defined by the input signal. It then cooperates with a second frequency correction signal (Yr2) to correct the frequency of an oscillator (VCO) supplying the output signal. The second frequency correction signal is obtained with the help of an adjustment signal (Yg) by integrating an error of the first frequency correction signal (Yr1) relative to said adjustment signal. The adjustment signal may itself be obtained by integrating a frequency error. The invention is particularly applicable to telecommunications systems.

REFERENCES:
patent: 4297728 (1981-10-01), Lowe
patent: 4404530 (1983-09-01), Stryer
patent: 4686689 (1987-08-01), Rorden
patent: 4745371 (1988-05-01), Haine
patent: 5319680 (1994-06-01), Port et al.
patent: 5570398 (1996-10-01), Smith

Affiliated with

Also associated with

Rating

Phase-locking method and a loop applying the method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locking method and a loop applying the method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locking method and a loop applying the method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1839461