Method of fabricating split-gate source side injection flash EEP

Details Method of fabricating split-gate source side injection flash EEP Method of fabricating split-gate source side injection flash EEP

1998-04-20

2000-05-23

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257319, 257320, 257321, 257322, 438267, H01L 29788

Patent

active

06066875&

ABSTRACT:
A split-gate source side injection flash EEPROM array structure and method of fabrication that utilizes the same polysilicon layer to form the control gate and the floating gate. Furthermore, there is a tunneling oxide layer underneath the floating gate, a gate oxide layer underneath the control gate, and that the tunneling oxide layer has a thickness smaller than the gate oxide layer. Since the control gate and the floating gate are formed on a silicon layer through the same patterning process, polysilicon spacers can be used to control the gap width between the control gate and the floating gate. Therefore, a reliable and reproducible flash cell array can be produced.

REFERENCES:
patent: 4855247 (1989-08-01), Ma et al.
patent: 4882707 (1989-11-01), Mizutani
patent: 5444279 (1995-08-01), Lee
patent: 5498559 (1996-03-01), Chang
patent: 5618742 (1997-04-01), Shone et al.

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