Non-volatile memory circuit

Details Non-volatile memory circuit Non-volatile memory circuit

1990-03-22

1995-06-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Noise suppression

365104, G11C 702

Patent

active

RE0349747

ABSTRACT:
A non-volatile memory circuit which may be formed on the same memory chip as a MOS integrated circuit for an electronic watch. The non-volatile memory circuit includes a power source and a high voltage application terminal for writing data. A non-volatile memory device is coupled between the power source and the high voltage application terminal. A voltage limiting circuit for limiting the voltage applied to the non-volatile memory is coupled between the power source and the high voltage application terminal. A current limiting circuit for limiting the current applied to the non-volatile memory is coupled between the high voltage application terminal and the non-volatile memory, whereby the non-volatile memory is protected from stray voltage and current writing data into the non-volatile memory. The invention may also be applied to an EEPROM arrangement in which the data may be read to or erased from the non-volatile memory without erroneous writing or erasure due to static noise or other outside noise.

REFERENCES:
patent: 3744036 (1973-07-01), Frohman-Bentchowsky
patent: 4589097 (1986-05-01), Ebihara
Dov Frohman-Bentchkowsky, "A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory", IEEE J. of Solid State Circuits, vol. SC-6, pp. 301-306, Oct. 1971.

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