Semiconductor device with double structured well

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257371, 257378, 257544, 257297, H01L 2702, H01L 2970

Patent

active

054463050

ABSTRACT:
A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

REFERENCES:
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patent: 5031019 (1991-07-01), Kosaka et al.
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patent: 5150184 (1992-09-01), Eklund
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Terrill et al., "A New Method for Preventing CMOS Latch-Up", IEDM, (1984), pp. 406-409.
"Multilayered Well Formation for Sub-0.5 .mu.m CMOS Devices Utilizing High Energy Ion Implantation", Extended Abstracts of the 21st Conference on Solid State Devices and Materials, by Kiyonori Ohyu et al., Tokyo, 1989, pp. 105-108.

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