Insulated-gate field-effect transistor structure and method

Details Insulated-gate field-effect transistor structure and method Insulated-gate field-effect transistor structure and method

1993-03-01

1999-09-07

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, H01L 2976

Patent

active

059491051

ABSTRACT:
An insulated-gate field-effect transistor 10 is formed on a semiconductor substrate 8. The source 12 and/or drain 20 junction region comprises a heavily doped region 14 (22), a non-overlapped lightly doped region 16 (24), and an overlapped lightly doped region 18 (26). The doping concentration and junction depth of the overlapped 18 and non-overlapped 16 lightly doped regions may be controlled and optimized independently. An insulating layer 50 is formed over a channel region 28 which separates the source 12 and drain 20, and also over the overlapped portions of the source 18 and drain 26. A gate 42 is formed over the insulating layer 50. Two exemplary methods of fabrication are disclosed in detail herein as well as other systems and methods.

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patent: 5047816 (1991-09-01), Cuevas

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