SRAM bus architecture and interconnect to an FPGA

Details SRAM bus architecture and interconnect to an FPGA SRAM bus architecture and interconnect to an FPGA

1998-03-16

2000-03-14

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710131, 326 37, 326 38, 326 39, 326 40, 36518501, 36518508, 36518511, H03K 19177

Patent

active

060386274

ABSTRACT:
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks without being further connected to the SRAM bussing architecture.

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