Cache reloading performance improvement through the use of early

Details Cache reloading performance improvement through the use of early Cache reloading performance improvement through the use of early

1997-07-07

2000-06-27

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711140, 711133, 711126, 711118, G06F 1200

Patent

active

060818727

ABSTRACT:
A DRAM for L2 cache is used in a computer memory hierarchy without compromising overall system performance. By proper organization and design, the DRAM L2 cache is many times larger than a SRAM implementation in the same technology, but without compromising overall system performance. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time. To achieve this, it is essential to minimize the total DRAM access time as much as possible by the use of early select techniques and pipelining.

REFERENCES:
patent: 5701503 (1997-12-01), Singh et al.
patent: 5732409 (1998-03-01), Ni
patent: 5796671 (1998-08-01), Wahlstrom
patent: 5801996 (1998-09-01), Seyyedy et al.
patent: 5832276 (1998-11-01), Feiste et al.

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