Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Patent
1997-12-30
2000-06-27
Monin, Jr., Donald L.
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
257904, 257393, 257334, H01L 2711
Patent
active
060810416
ABSTRACT:
A static random access memory (SRAM) cell includes a substrate having first and second semiconductor layers, the second semiconductor layer being on the first semiconductor layer, active regions of first and second access transistors in the second semiconductor layer, gate electrodes of the first and second access transistors on the active regions, gate electrodes of first and second drive transistors in first terminals of the first and second access transistors, respectively, the gate electrodes penetrating the second semiconductor layer, first and second load resistors electrically contacting the first terminals of the first and second access transistors, respectively, and first and second bit lines electrically contacting second terminals of the first and second access transistors, respectively.
REFERENCES:
patent: 5122846 (1992-06-01), Haken
patent: 5298764 (1994-03-01), Yamanaka et al.
patent: 5489790 (1996-02-01), Lage
T. Kikuchi, et al., "A 0.35 .mu.m ECL-CMOS Proces Technolog on SOI for 1ns Mega-bits SRAM'S with 40ps Gate Array" 1995; IEDM 95 pp. -923-926.
LG Semicon Co. Ltd.
Monin, Jr. Donald L.
Pham Hoai
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