MOS field effect transistor having source/drain regions surround

Details MOS field effect transistor having source/drain regions surround MOS field effect transistor having source/drain regions surround

1991-01-04

1996-07-16

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257403, 257404, H01L 2978

Patent

active

055369570

ABSTRACT:
Disclosed is a MOSFET for controlling the flow of a large number of carriers from one source/drain region to the other source/drain region by applying a voltage to a gate. This MOSFET includes a semiconductor substrate and a transistor. The transistor includes a gate provided on the semiconductor substrate, one source/drain region and the other source/drain region both having a first conductivity type. The MOSFET includes first and second wells of a second conductivity type formed apart from each other on opposite sides of the gate in the main surface of the semiconductor substrate. The first well is such a small well as to accommodate only one source/drain region, while the second well is such a small well as to accommodate only the other source/drain region. The one source/drain region and the other source region are formed in the first and second wells, respectively. No distortion due to thermal stresses remains in the resultant MOSFET, and consequently a highly reliable MOSFET is obtained.

REFERENCES:
patent: 3437891 (1969-04-01), Yamashita
patent: 3821776 (1974-06-01), Hayashi et al.
patent: 3988761 (1976-10-01), Kanazawa
patent: 4597824 (1986-07-01), Shinada
patent: 4924277 (1990-05-01), Yamane et al.
patent: 4931408 (1990-06-01), Hshieh
patent: 4979001 (1990-12-01), Alter
patent: 4990978 (1991-02-01), Kondoh
"A New Twin-Well CMOS Process Using Nitridized-Oxide-LOCOS (NOLOCOS) Isolation Technology", Tsai et al., IEEE Electron Device Letters, vol. 10, No. 7, Jul. 1989.

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