Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-08-21
2000-06-27
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438627, 438628, 438633, 438634, 438637, 438650, 438686, 438666, 438700, 438738, 438740, H01L 214763
Patent
active
060806559
ABSTRACT:
A method and substrate structure for fabricating highly conductive components on microelectronic devices. In one embodiment in accordance with the principles of the present invention, a first dielectric layer is formed over a base layer of a substrate, a second dielectric layer is deposited onto the first dielectric layer, and a third dielectric layer is deposited onto the second dielectric layer. The first, second and third dielectric layers define a dielectric stratum in which the first and second dielectric layers may be selectively etchable from one another so that the second dielectric layer etches at a faster rate than the first layer in the presence of a selective etchant. After the dielectric layers are deposited onto the substrate, a void is etched through the second and third dielectric layers. The void may be etched in a two part process in which a non-selective etchant etches through the third dielectric layer to an intermediate level in the second dielectric layer, and then a selective etchant etches through the remaining portion of the second dielectric layer to the first dielectric layer. The third dielectric layer is subsequently covered with a conductive material, and the void is filled with a portion of the conductive layer. The substrate is then planarized to the third layer to form a conductive component in the void. The third dielectric layer generally has a lower polishing rate than the conductive layer so that the third dielectric layer acts as a polish-stop layer for the planarizing process. Although the method is applicable to forming virtually any type of conductive component on a substrate, it is particularly useful for forming gold components in contact holes and/or trenches.
REFERENCES:
patent: 5300813 (1994-04-01), Joshi et al.
patent: 5371047 (1994-12-01), Greco et al.
patent: 5403779 (1995-04-01), Joshi et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5612254 (1997-03-01), Mu et al.
patent: 5614765 (1997-03-01), Avanzino et al.
patent: 5726100 (1998-03-01), Givens
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5858877 (1999-01-01), Dennison et al.
patent: 5877076 (1999-03-01), Dai
patent: 5882996 (1999-03-01), Dai
patent: 5926732 (1999-07-01), Matsuura
patent: 5933761 (1999-08-01), Lee
patent: 5935762 (1999-08-01), Dai et al.
Givens John H.
Lane Richard H.
Garley Lynne A.
Micro)n Technology, Inc.
Niebling John F.
LandOfFree
Method for fabricating conductive components in microelectronic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating conductive components in microelectronic , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating conductive components in microelectronic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1784224