Process for patterning local interconnects

Details Process for patterning local interconnects Process for patterning local interconnects

1986-03-07

1987-04-14

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29571, 29576W, 29591, 156644, 156646, 156653, 156656, 1566591, 20419232, 252 791, 427 89, C23F 102, B44C 122, H01L 21306, C03C 1500

Patent

active

046576282

ABSTRACT:
A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.

REFERENCES:
patent: 3387952 (1968-06-01), Chapelle
patent: 4593454 (1986-06-01), Baudrant et al.

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