Method of laying out interconnections

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

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716 13, 716 7, G06F 1750

Patent

active

060802065

ABSTRACT:
To implement a method of laying out interconnections, which is capable of reducing a skew value of a predetermined signal and a delay in predetermined signal to the utmost, a region intended for a wiring layout employed in a CAD system is divided into a plurality of subregions and wiring regions dedicated to the predetermined signal in the respective subregions are set. The number of driver's stages in the respective subregions is set and the region is enlarged with the adjacent subregions identical in number of driver's stages as virtual subregions. Thus, the layout of wiring between the subregions is set.

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