Semiconductor memory

Details Semiconductor memory Semiconductor memory

1998-05-26

1999-05-18

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, G11C8/00

Patent

active

059056916

ABSTRACT:
A command register recognizes a batch-write test mode and outputs to a clock generating circuit signals indicating the recognition of the mode. In the batch-write test mode, the clock generating circuit generates a clock signal having a longer cycle than a clock signal generated in a normal operation mode. The clock signal is supplied to a row decoder (word line potential control circuit) to control the operation of the row decoder, so that the row decoder supplies a sufficient write potential to all word lines.

REFERENCES:
patent: 5575715 (1996-11-01), Williams et al.
patent: 5600605 (1997-02-01), Schaefer
patent: 5600606 (1997-02-01), Rao
patent: 5612926 (1997-03-01), Yazawa et al.
patent: 5673233 (1997-09-01), Wright et al.

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