Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-09-29
1999-05-18
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Testing
365 96, 36518903, 365200, 3652257, 36523008, 371 111, G11C7/00
Patent
active
059056835
ABSTRACT:
Therefore, according to the present invention, one or more bond pads of a memory device are connected to a corresponding address buffer or address buffers by a selection circuit which selectively allows the address buffer to ignore a signal on the bond pad. In order to define a smaller density memory device, the signal on the bond pad is ignored, and the selection circuit internally forces a logic state on the address buffer which points to the desired smaller density memory device. The memory devices and the smaller density memory devices are packaged and bonded identically and then sorted and branded such that it is not necessary to use the double inking technique. The present invention may be applied to a plurality of bond pads and corresponding address buffers. According to a preferred embodiment of the invention, the selection circuit has of a plurality of fuses which may be selectively blown to cause the address buffer to ignore a signal on the bond pad. Nonvolatile devices such as EPROM, EEPROM, Flash EPROM, or PROM devices may also be used instead of fuses. The present invention can make use of ESD transistors, or nonvolatile devices, and fuses.
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Galanthay Theodore E.
Jorgenson Lisa K.
Larson Renee M.
ST Microelectronics, Inc.
Yoo Do Hyun
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