Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1991-12-12

1993-11-02

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

36518907, 365208, G11C 700

Patent

active

052589587

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a semiconductor memory device.
A conventional semiconductor memory device constructed so that a data readout speed is caused to be faster will be described with reference to FIG. 54. This semiconductor memory device comprises two memory cell arrays of the same structure to allow a pair of cells to be operative at the same time to read out data therefrom. More particularly, this memory device is of an EPROM structure in which floating gate type MOSFETs are arranged in a matrix form as respective memory cells. Memory cells T11, T12, . . . , Tmn and memory cells TT11, TT12, . . . , TTmn comprised of floating gate type MOSFETs function to store either of binary data. For storing data of one bit, two memory cells such as memory cells T11 and TT11, and T12 and TT12 and so on are used as a pair or a set.
Gates of memory cells belonging to respective the same rows are connected to word lines WL1, WL2, . . . , WLm. Further, drains of memory cells belonging to respective columns are connected to bit lines BL1, BL2, . . . , BLn or bit lines BBL1, BBL2, . . . , BBLn. A memory cell is selected by a column decoder 4 and a row decoder 5. The column decoder 4 selects arbitrary bit lines by selectively driving column gate transistors CG1, CG2, . . . , CGn and column gate transistors CCG1, CCG2, . . . , CCGn.
Transistors Q2 and Q4 serve to charge these bit lines BL and BBL, respectively. Further, transistors Q3 and Q6 serve to make a connection of bit lines BL and BBL to place them in an equipotential state (hereinafter referred to as "equalization"). Transistors Q2-Q4 and Q6 become operative when a pulse signal .phi. is a logic "1". Transistors Q1 and Q5 serve to allow a predetermined current to flow to the bit line BL and the bit line BBL, respectively, with a view to making a compensation such that potentials on the bit line BL and the bit line BBL charged by the transistors Q2 and Q4, respectively, are not lowered by a leak current, etc., thus to charge bit lines.
Further, transistors Q7, Q8, Q9 and Q10 serve to suppress elevations in the drain voltages of respective memory cells so that each drain voltage is not above a predetermined level, thus to improve reliability of the memory cells.
A sense amplifier 10 serves to compare, with each other, changes in potentials on the bit line BL and the bit line BBL which are respectively given as voltages VIN1 and VIN2 to thereby sense data stored in the memory cells to output its result to an external equipment (not shown) as a signal D.
In the memory device thus constructed, how the sense amplifier 10 reads out data stored in the memory cells will now be described.
The storage of data in the memory cell is conducted depending upon whether or not electrons are injected into the floating gate. The memory cells in which electrons are injected into the floating gate are maintained in an OFF state even when a signal of logic "1" level is applied to the gates thereof. In contrast, the memory cells in which no electron is injected into the floating gate are turned on when that signal is applied. More particularly, a pair of memory cells have a relationship such that they are in states opposite to each other such that if electrons are injected into the floating gate of, e.g., one memory cell T11, no electron is injected into the other memory cell TT11.
For example, a word line WL1 is placed at a predetermined potential by the row decoder 5. Further, the column gate transistor CG1 and the column gate transistor CCG1 become conductive by the column decoder 4. A pair of memory cells, e.g., memory cells T11 and TT11 are thus selected.
Data stored in the memory cells T11 and TT11 thus selected are read by the sense amplifier 10. This reading operation is caused to be fast by carrying it in a manner described below. An explanation thereof will now be made with reference to FIG. 55.
When an equalization signal .phi. of "1" is applied to each gate of precharging transistors Q2 and Q4 and equalizing transistors Q3 and Q6, these transistors become cond

REFERENCES:
patent: 4301518 (1981-11-01), Klaas
patent: 5148063 (1992-09-01), Hotta
Richard Zeman et al., "A 55ns CMOS EEPROM", IEEE ISSCC Digest of Technical Papers, pp. 144-145, 1984.

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