High voltage lateral enhancement IGFET

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257343, 257409, 257603, H01L 2976, H01L 2994, H01L 31062, H01L 2990

Patent

active

052296334

ABSTRACT:
A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity type.

REFERENCES:
patent: 4614959 (1986-09-01), Nakagawa
patent: 4626879 (1986-12-01), Colak
patent: 4730208 (1988-03-01), Sugino et al.
patent: 4947232 (1990-08-01), Ashida et al.
patent: 5055896 (1991-10-01), Williams et al.
patent: 5086332 (1992-02-01), Nakagawa et al.
patent: 5128730 (1992-07-01), Coe et al.

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