System for preemptive bus master termination by determining term

Details System for preemptive bus master termination by determining term System for preemptive bus master termination by determining term

1995-08-18

1998-06-16

Lee, Thomas C.

395852, G06F 1328

Patent

active

057686220

ABSTRACT:
A PCI bus master which determines the termination characteristics of one or more PCI targets coupled to the bus and uses this information to eliminate the wait states that are incurred during a bus cycle when a target device attempts to perform a data phase termination. According to the present invention, at initialization the bus master performs burst cycles on arbitrary address boundaries and stores the target's termination boundaries and cycle conditions. The bus master uses this information during burst transfers to initiate the data phase termination prior to the target, thus preempting the target from performing this termination. This operates to maintain the target's maximum burst capabilities while also eliminating the rearbitration wait states incurred when the bus master receives a termination from the target device. This also allows the bus master to chain together fast back-to-back PCI cycles while retaining bus ownership.

REFERENCES:
patent: 4995056 (1991-02-01), Frogg Jr. et al.
patent: 5377325 (1994-12-01), Chan
patent: 5584033 (1996-12-01), Barrett et al.
patent: 5623633 (1997-04-01), Zeller et al.

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