Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-08-19
1998-06-16
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711206, 711209, G06F 932
Patent
active
057685746
ABSTRACT:
A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to selectively enable condition flag modification for instructions. An instruction which modifies the condition flags and a branch instruction intended to branch based on the condition flags set by the instruction may be separated by numerous instructions which do not modify the condition flags. When the branch instruction is decoded, the condition flags it depends on may already be available. In another embodiment of the present microprocessor, the segment register override bytes are used to select between multiple sets of condition flags. Multiple conditions may be retained by the microprocessor for later examination. Conditions which a program utilizes multiple times in a program may be maintained while other conditions may be generated and utilized.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4050094 (1977-09-01), Bourke
patent: 4109311 (1978-08-01), Blum et al.
patent: 4385352 (1983-05-01), Bienvenu
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4835734 (1989-05-01), Kodaira et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4926322 (1990-05-01), Stimac et al.
patent: 4972338 (1990-11-01), Crawford et al.
patent: 5109334 (1992-04-01), Kamuro
patent: 5125087 (1992-06-01), Randell
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5226132 (1993-07-01), Yamamoto et al.
patent: 5274834 (1993-12-01), Kardach et al.
patent: 5293592 (1994-03-01), Fu et al.
patent: 5303358 (1994-04-01), Baum
patent: 5321836 (1994-06-01), Crawford et al.
patent: 5375213 (1994-12-01), Arai
patent: 5438668 (1995-08-01), Coon et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5560032 (1996-09-01), Nguyen et al.
patent: 5561784 (1996-10-01), Chen et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," Byte, Jan. 1996, 4 pages.
IEEE Micro, vol. 13, No. 5, Oct. 1, 1993, pp. 24-36, XP000397921, Makoto Awaga et al.: "The VP 64-Bit Vector Coprocessor: A New Implementation of High-Performance Numerical Computation".
Christie David S.
Dutton Drew J.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Lall Parshotam S.
Patel Gautam R.
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