Dynamic random access memory capable of simultaneously writing i

Details Dynamic random access memory capable of simultaneously writing i Dynamic random access memory capable of simultaneously writing i

1999-05-27

2000-11-28

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Parallel read/write

365190, 36523006, G11C 700

Patent

active

06154406&

ABSTRACT:
Where a first bit line pair comprises a first bit line and a second bit line, a first memory cell is located at an intersection between a selected word line and the first bit line. Where a second bit line pair comprises a third bit line and a fourth bit line, a second memory cell is located at an intersection between the selected word line and the fourth bit line. A data line pair comprises a first data line and a second data line. A first column switch comprises a first transistor connected between the first bit line and the first data line and a second transistor connected between the second bit line and the second data line. A second column switch comprises a third transistor connected between the third bit line and the first data line and a fourth transistor connected between the fourth bit line and the second data line. A column decoder turns on one of the first column switch and the second column switch in a normal-write mode, and turns on both the first column switch and the second column switch in a block-write mode. In the block-write mode, a potential of the first bit line and a potential of the fourth bit line are complementary to each other. Identical data is written to the first memory cell and the second memory cell.

REFERENCES:
patent: 5740212 (1998-04-01), Oh et al.
patent: 5828617 (1998-10-01), Knaack

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