Semiconductor memory device having a delay circuit set according

Details Semiconductor memory device having a delay circuit set according Semiconductor memory device having a delay circuit set according

1999-11-19

2000-11-28

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Signals

36518905, 36518908, 365233, 3652335, 36523003, 365 63, 365226, G11C 710

Patent

active

061543969

ABSTRACT:
A delay circuit that delays a signal for controlling data read/write is composed of inverters, capacitors, and switches. The delay time that the delay circuit provides is set by selectively changing over the switches according to the storage capacity of a memory macro. Thus, the delay time most suitable for the storage capacity of the memory macro can be set, which allows the data read/write operation to be speeded up.

REFERENCES:
patent: 5698876 (1997-12-01), Yabe et al.
patent: 5881008 (1999-03-01), Becker
Yabe et al., "A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator", ISSCC 98, Feb. 5, 1998, pp. 72-73, 415.
IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998; "A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator", Tomoaki Yabe, et al., pp. 1752-1757 .

Affiliated with

Also associated with

Rating

Semiconductor memory device having a delay circuit set according does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having a delay circuit set according, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a delay circuit set according will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1732245