Output buffer

Details Output buffer Output buffer

1999-06-02

2000-11-28

Nguyen, Viet Q.

Electronic digital logic circuitry

Interface

Logic level shifting

326 24, 326 25, 326 26, 326 33, 326 34, 326 57, H03K 19003

Patent

active

061540587

ABSTRACT:
An output buffer includes a p-channel transistor, and first and second n-channel transistors. The p-channel transistor has one of a source and drain which is connected to power supply and the other which is connected to an output node connected to an output terminal. The first n-channel transistor has one of a source and drain which is grounded and the other which is connected to the output node. The second n-channel transistor is series-connected to the p-channel transistor between a power supply and the output node and receives at a gate a power supply potential level which rises at substantially the same time as the power supply upon ON operation.

REFERENCES:
patent: 5396128 (1995-03-01), Dunning
patent: 5438278 (1995-08-01), Wong et al.
patent: 5500610 (1996-03-01), Burstein
patent: 5852382 (1998-12-01), Lentini et al.
patent: 5959481 (1999-09-01), Donnelly et al.
patent: 6005413 (1999-12-01), Schmitt
patent: 6040711 (2000-03-01), Airaksinen et al.

Affiliated with

Also associated with

Rating

Output buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1729535