Multiplier fabric for use in field programmable gate arrays

Details Multiplier fabric for use in field programmable gate arrays Multiplier fabric for use in field programmable gate arrays

1998-03-27

2000-11-28

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 34, 326 37, 326 40, 326 41, 326 44, 326 45, G06F 738

Patent

active

061540498

ABSTRACT:
A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of multiplier tiles. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of multiplier tiles. However, selected CLEs can also be coupled to selected multiplier tiles, thereby creating a relatively high density multiplier circuit. Each of the multiplier tiles includes a multiplier array having a predetermined size (e.g., a 2.times.4 bit multiplier array). The multiplier tiles can be selectively coupled to one another, such that the multiplier arrays are connected to form a relatively large multiplier circuit. The desired multiplier and multiplicand bits are routed into the multiplier tiles from associated CLEs. Similarly, the resulting product bits are routed from the multiplier tiles to associated CLEs. In this manner, the FPGA is capable of implementing a relatively large multiplier circuit in an efficient manner.

REFERENCES:
patent: 5796269 (1998-08-01), New
patent: 5880597 (1999-03-01), Lee
patent: 5898319 (1999-04-01), New
patent: 5910732 (1999-06-01), Trimberger
"The Programmable Logic Data Book", published Sep., 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 4-5 to 4-96.
"The Programmable Logic Data Book" published 1994, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 2-5 to 2-102.

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