Method for manufacturing capacitor of semiconductor memory devic

Details Method for manufacturing capacitor of semiconductor memory devic Method for manufacturing capacitor of semiconductor memory devic

1995-07-07

1997-05-20

Tsai, Jey

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

H01L 2170, H01L 2700

Patent

active

056311850

ABSTRACT:
A method for manufacturing a capacitor of a semiconductor memory device is provided. A first insulating layer and a second insulating layer are formed in sequence on a semiconductor substrate on which a transistor including a source region, a drain region and a gate electrode, and a buried bit-line surrounded by insulating layer are formed. Then, a contact hole is formed by sequentially etching the layers stacked on the source region, by which the source region of the transistor is exposed, and a spacer made of an insulating substance is formed inside the contact hole, and a first conductive layer is formed on the whole surface of the resultant. Next, the first conductive layer and second insulating layer are etched, and a second conductive layer is formed on the whole surface of the resultant, and a storage electrode is formed by etching the second conductive layer using the first conductive layer as a mask. According to the method, the step for forming the contact hole is very simple and less photolithography steps are required since the first conductive layer is used as a mask for etching the second conductive layer, thereby simplifying the manufacturing process.

REFERENCES:
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5286668 (1994-02-01), Chou
patent: 5422295 (1995-06-01), Choi et al.

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