Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-07-17
2000-03-14
Guay, John
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
G06F 1518, H01L 29788
Patent
active
060376260
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
In modern data processing, in particular in video and audio applications, neural networks are playing an increasing role. The fundamental elements of these neural networks are neurons, in which, in the simplest case, a number of inputs act with variable weight on a single output, the signal of the latter respectively assuming a different logic state if the weighted sum of all inputs exceeds or falls below a specific threshold. Neural networks have some similarities with brains, since, in particular, they are capable of learning and the quality of their results can be improved constantly by repeated practice. At present, neurons are for the most part produced using software. However, for faster and more complex applications of neural networks, it is in many cases necessary to implement neurons using hardware, but this has so far raised problems in adaptability to a variety of applications. Applications which are further aspired to, for example in image processing, require very high processing speeds, which in practice can only be achieved using hardware solutions.
IEEE Transactions on Electron Devices, Vol. 39, No. 6, June 1992, pages 1444 to 1454, has already disclosed a component which, with a very small surface area, has important partial functions, for example the logical coupling of a plurality of inputs, and the formation of a threshold value. A disadvantage in this case is that the individual inputs cannot be weighted differently, or that the weighting of the inputs cannot be altered flexibly.
European patent applications 0 685 808 A and 0 657 934 A respectively disclose a semiconductor neuron, whereby an input electrode comprising a plurality of sub-electrodes is capacitatively coupled to a floating gate, whereby the inputs of the semiconductor neuron can be connected to a plurality of sub-electrodes, so that, for the overall area of these inputs, the weightings of all neuron inputs can be modified. In FIG. 8 of the 0 685 808 A application, for example, the input Ci-1 is connected to two electrodes of the two last stages, whereas the two other signal inputs are only respectively connected to one electrode. In FIG. 1c of the 0 657 934 A application, for example, the input electrodes A1-A3 are connected to one another, whereas the input electrodes C1-C4 are connected to one another.
SUMMARY OF THE INVENTION
The object of the invention is therefore to provide a semiconductor neuron and a corresponding drive, such that the semiconductor neuron, with a small chip area and a high processing speed, permits variable weighting of the inputs.
In general terms the present invention is a semiconductor neuron, in which at least one input electrode, consisting of a plurality of partial electrodes, is coupled capacitively for signal transmission to a floating gate whose potential controls the current of a MOS field effect transistor. A respective neuron input can be connected to partial electrodes of the plurality of partial electrodes such that the total surface area of the partial electrodes connected to the respective neuron input corresponds to a respective weight of the neuron input. Sub-electrodes of the input electrodes are connected to neuron inputs via multiplexers.
Advantageous developments of this embodiment of the present invention are as follows.
Partial electrodes of a respective neuron have different electrode surface areas.
A respective neuron is driven by a respective control circuit, all control circuits being supplied from a single controller with addresses, data and a clock signal.
A respective control circuit connected to a respective neuron is equipped with an address decoder, a data connection unit, a clock connection unit and a shift register. It is possible for the data and the clock signal to be fed as a function of the address to the shift register which, for its part, produces control signals for the multiplexers of a respective neuron.
The respective control circuit is supplied by the controller with addresses and data in such a way that the total surfac
REFERENCES:
patent: 5498888 (1996-03-01), Ozawa
patent: 5587668 (1996-12-01), Shibata et al.
patent: 5937399 (1999-08-01), Ohmi et al.
patent: 5973535 (1999-10-01), Shibata et al.
IEEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992, Tadashi Shibata et al, "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," pp. 1444-1455.
IEICE Trans. Electron, vol. E76-C, No. 3, Mar. 1993, Invited Paper, Special Issue on Multiple-Valued Integrated Circuits, T. Shibata et al, "Neuron MOS Voltage-Mode Circuit Technology for Multiple-Valued Logic," pp. 347-356.
IEICE Trans. Electron, vol. E77-C. No. 7, Jul. 1994, Paper, Special Issue on Super Chip for Intelligent Integrated Systems, T. Ohmi et al, "The Concept of Four-Terminal Devices and Its Significance in the Implementation of Intelligent Integrated Circuits", pp. 1032-1041.
Thewes Roland
Weber Werner
Guay John
Siemens Aktiengesellschaft
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