DRAM cell with transfer device extending along perimeter of tren

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257301, 257302, 257303, H01L 27108

Patent

active

060376201

ABSTRACT:
A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap. Also disclosed herein are methods of forming a semiconductor memory cell and of forming groups of semiconductor memory cells. A method of forming a semiconductor memory cell includes the steps of forming a storage capacitor in a deep trench etched into a substrate including a monocrystalline semiconductor; forming a shallow trench isolation (STI) region at least partially overlaying the deep trench; forming and outdiffusing a strap in a sidewall of the deep trench; forming first spacers on exterior surfaces of the STI region and deep trench; etching, selective to the monocrystalline semiconductor; removing the first spacers to expose a mesa region of monocrystalline semiconductor located on exterior sidewalls of the deep trench and STI region and conductively connected to the strap; adjusting dopant concentrations in at least a portion of the mesa region to form a channel region and source/drain regions; forming a gate dielectric over at least the channel region; depositing a gate conductor over the channel region; and forming a bitline contact to a first of the source/drain regions.

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T. Ozaki, et al., "0.228.mu.m2 Trench Cell Technologies with Bottle-Shaped Capacitor for 1Gbit DRAMs", 1995, IEEE, pp. 27.3.1-27.3.4.

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