Semiconductor memory having stacked capacitors and MOS transisto

Details Semiconductor memory having stacked capacitors and MOS transisto Semiconductor memory having stacked capacitors and MOS transisto

1991-08-09

1994-04-26

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Capacitors

257302, 257303, 257330, 257908, H01L 2978

Patent

active

053073100

ABSTRACT:
A dynamic random access memory comprises a p-type semiconductor substrate and a plurality of first n-type diffused regions embedded in the substrate so that they extend along a first axis of the substrate parallel with first and second, opposed major surfaces of the substrate to form parallel bit lines. A matrix array of insulated gate electrodes extend along a second axis of the substrate normal to the first axis from the first major surface into the first n-type diffused regions, so that those of the insulated gate electrodes which are arranged along rows of the matrix are connected together by the parallel bit lines. Second n-type diffused regions are embedded in the substrate adjacent to the first major surface as well as to corresponding ones of the insulated gate electrodes. Parallel conductors extend along a third axis of the substrate for electrically connecting those of the gate electrodes which are arranged along columns of the matrix array to respective word lines, the third axis being perpendicular to both of the first and second axes. Capacitors are stacked on the insulated gate electrodes, respectively. Each of the capacitors has a cell electrode coupled to one of the second n-type diffused regions, a common electrode and a charge storage layer interposed therebetween.

REFERENCES:
patent: 4716548 (1987-12-01), Mochizwki
patent: 4833516 (1989-03-01), Hwang et al.
patent: 4949138 (1990-08-01), Nishimura
patent: 5034785 (1991-07-01), Blanchard
patent: 5100823 (1992-03-01), Yamada

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