Sense amplifier and method for sensing the outputs of static ran

Details Sense amplifier and method for sensing the outputs of static ran Sense amplifier and method for sensing the outputs of static ran

1990-02-08

1991-02-05

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

307530, G11C 1300

Patent

active

049911414

ABSTRACT:
A sense amplifier (10) is provided for with use with a static random access memory. Cascode preamplifier transistors (20a, 20b) convert the complementary currents appearing on bitlines (14a, 14b) coupled to the complementary outputs BIT and BIT of a memory cell (12). The currents are converted into differential voltages and amplified into emitter coupled logic compatible voltages which are output from sense amplifier (10) on DATA line (30a) and DATA line (30b). In a preferred embodiment, a first feedback loop is provided from DATA line (30b) to preamplifying transistor (20a) and a second feedback loop is provided from DATA line (30a) to preamplifier transistor (20b).

REFERENCES:
patent: 4509147 (1985-04-01), Tanimura
Tran, H., et al., "An 8ns Battery Back-Up Submicron BiCMOS 256K ECL SRAM," ISSCC Digest of Technical papers, pp. 188-189, Feb., 1988.
Yang, T., et al., "A 4-ns 4Kx1-bit Two-Port BiCMOS SRAM," IEEE J. Solid-State Circuits, vol. 23, No. 5, pp. 1030-1040, Oct., 1988.

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