Trench surrounded metal pattern

Details Trench surrounded metal pattern Trench surrounded metal pattern

1997-10-30

1999-06-22

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438926, 438669, 438699, H01L 2128

Patent

active

059152010

ABSTRACT:
A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. The dummy metal areas are also etched into island pieces with size similar to the feature size. Narrow trenches with the same constant width and depth surround the dummy metal islands. A dielectric layer is deposited over the metal lines and dummy metal islands wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines. The extra trenches between the dummy metal islands further lower parasitic capacitance and decrease the possibility of shorting between metal lines as well as reduce the loading effect during metal etching.

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