Synchronized clocking disable and enable circuit

Details Synchronized clocking disable and enable circuit Synchronized clocking disable and enable circuit

1993-06-01

1995-05-09

Callahan, Timothy P.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular output circuits for counter

377 81, 377 79, 327142, 327292, G11C 1928

Patent

active

054147450

ABSTRACT:
A clocking disable and enable circuit is provided having an input for receiving a clocking signal and another input for receiving a disable/enable signal. The disable and enable circuit provides a clocking disable/enable output from the circuit which is synchronized with the clocking signal during times in which the disable/enable signal is not activated. At times during which the disable/enable signal is activated, the clocking disable/enable signal transitions after at least a one half clocking period to a steady state value (either high or low voltage level). After the disable/enable signal becomes inactive again, clocking disable/enable signal automatically resynchronizes to the clocking signal. The clocking disable and enable circuit herein is well suited for providing glitch-free transition between a clocking state and a steady state to a synchronized digital or analog circuit which depends upon clocking synchronization for its operation. The clocking disable and enable circuit herein is also well suited for providing temporary halt to the connected digital or analog circuit as well as providing periods of selective demodulation associated with frequency tracking communication systems.

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patent: 5208546 (1993-05-01), Nagaraj et al.
patent: 5239206 (1993-08-01), Yanai

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