Memory control device

Details Memory control device Memory control device

1992-07-30

1995-05-09

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

36523005, 365233, 3652385, 395725, G11C 700

Patent

active

054146666

ABSTRACT:
A memory control device adaptable to various demands and using a standard DRAM. A memory interface for outputting an address of the memory and controllably reading and writing is connected to the memory. A plurality of input and output ports are connected to the memory interface through a local bus. A host interface is connected to the memory interface through the local bus. A refresh control refreshes the memory through the memory interface. An arbitration structure arbitrates the required access to memory between the refresh control means, the input and output ports and the host interface.

REFERENCES:
patent: 4493036 (1985-01-01), Bondreau et al.
patent: 4796232 (1989-01-01), House
patent: 4956820 (1990-09-01), Hashimoto
patent: 5216635 (1993-06-01), Kass et al.
N. Siddique, 100 MHz DRAM Controller Sparks Multi-Processor Design, Electronic Design, vol. 34, No. 22, Sep. 1986 pp. 138-141.
Reiner et al., "VLSI Development of a Global Memory Interfaced Controller", 1990 Military Commnications Conference, Oct. 3, 1990, p. 254.
D. Bursky, `Triple-port DRAM fuels graphics displays`, Electronic Design, vol. 35, No. 10, Apr. 1987, pp. 53-54.
"To Control an Image Memory in Various Way", Ryohei Kumagai, 7, vol. 2, No. 7 With English Translat ion.

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