Short circuit power optimization for CMOS circuits

Details Short circuit power optimization for CMOS circuits Short circuit power optimization for CMOS circuits

1995-01-19

1997-03-18

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

327170, 364489, 364490, H03K 190948, G06F 1500

Patent

active

056126360

ABSTRACT:
An electronic circuit is constructed from a plurality of logic gates, each logic gate including a logic input, a logic output and a pair of power supply inputs, and each logic gate being operable to permit short circuit current to flow between the power supply inputs thereof during a logic level transition at the logic input thereof. A first logic gate (L) and a second logic gate (D) are provided with the output of the second logic gate connected to the input of the first logic gate, and the drive strength of the second logic gate is selected as a function of the short circuit current permitted by the first logic gate.

REFERENCES:
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4727266 (1988-02-01), Fujii et al.
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 5179298 (1993-01-01), Hirano et al.
patent: 5349534 (1994-10-01), Fujiki et al.
H.J.M. Veendrick, "Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 4, Aug. 1984, pp. 468-473.

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