Semiconductor device having CMOS transistors

Details Semiconductor device having CMOS transistors Semiconductor device having CMOS transistors

1996-02-15

1998-11-24

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

With inversion-preventing shield electrode

257372, 257394, H01L 2358

Patent

active

058411852

ABSTRACT:
A semiconductor device comprises a semiconductor substrate having N- and P-channel regions formed therein; a plurality of first transistors formed in the N-channel region; a first field shield element-isolation structure having a first shield plate electrode and formed in the N-channel region for isolating the first transistors from each other; a plurality of second transistors formed in the P-channel region; and a second field shield element-isolation structure having a second shield plate electrode electrically connected to the first shield plate electrode and formed in the P-channel region for isolating the second transistors from each other; wherein respective values of a threshold voltage V.sub.tN of a parasitic transistor formed in a field region of the N-channel region, a threshold voltage V.sub.tP of a parasitic transistor formed in a field region of the P-channel region and a potential V.sub.sP of the first or second shield plate electrode are determined so as to meet V.sub.tN -V.sub.tP >V.sub.cc -V.sub.ss and V.sub.tN >V.sub.sP -V.sub.ss >V.sub.tP +V.sub.cc -V.sub.ss, where V.sub.ss is a potential of the source of the first transistor, V.sub.cc is a potential of the source of the second transistor and V.sub.cc >V.sub.ss. Further, a method for manufacturing a semiconductor device as above-mentioned wherein the surface impurity concentration of at least one of the P-channel region and the N-channel region is determined by a desired threshold voltage of the MOS transistor formed in that region.

REFERENCES:
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patent: 5463238 (1995-10-01), Takahashi et al.
patent: 5498898 (1996-03-01), Kawamura
patent: 5510638 (1996-04-01), Lancaster et al.
patent: 5521419 (1996-05-01), Wakamiya et al.
Wakayima et al., Fully Planarized 0.5um Technologies for 16M DRAM, IEDM88, 1988, IEEE pp. 246-249.

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