Electrical computers and digital processing systems: memory – Address formation – Slip control – misaligning – boundary alignment
Patent
1996-04-10
1999-06-08
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Slip control, misaligning, boundary alignment
711167, 711118, 395855, 3952003, 3952005, 395287, G06F 1328
Patent
active
059111518
ABSTRACT:
A computer processor (110) automatically generates block-size operand references during execution of standard instructions. As such a standard instruction is executed, the processor (110) continually examines the number of bytes to be moved (342) and the relative alignment of the operand address (352). At any time during instruction execution, if the operand address is zero modulo the block size, and at least a block sized number of bytes remain to be moved (354), the operand transfer is marked as a block-sized reference.
This provides a convenient method for generating block-sized memory references to/from the targeted address space, independent of cache modes such as copyback, write-through, or non-cacheable. This may produce burst accesses, maximizing performance of the data transfer. Additionally, cache memory writes can be optimized to avoid cache line fill reads.
The result is that such standard instructions become the optimal method of transferring data from a source to a destination without the need for special instructions.
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Circello Joseph C.
Hardage, Jr. James N.
Harris Glen A.
Chan Eddie P.
Heyden Bruce E.
Motorola Inc.
Nguyen T. V.
Toler Jeffrey G.
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