Polysilicon polish for patterning improvement

Details Polysilicon polish for patterning improvement Polysilicon polish for patterning improvement

1997-09-02

1999-06-08

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438592, 438692, 438693, H01L 2144

Patent

active

059111119

ABSTRACT:
A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.

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