Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-08-19
1999-11-30
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 30, 714725, 714733, 714734, G06F 1100
Patent
active
059960914
ABSTRACT:
A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally. The novel method further comprises instructing the CPLD to program again, or overprogram, the program data into the memory location if the program data matches the verify data. The novel method further comprises reprogramming the program data into the memory location if the program data does not match the verify data.
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Johnson David L.
Jones Christopher W.
Cypress Semiconductor Corp.
Le Dieu-Minh T.
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