Method and apparatus for multiple row activation in memory devic

Details Method and apparatus for multiple row activation in memory devic Method and apparatus for multiple row activation in memory devic

1998-09-02

2000-02-08

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Testing

371 101, 371 211, G11C 2900

Patent

active

060234342

ABSTRACT:
A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.

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