Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1987-08-20
1989-03-07
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365 96, 365189, 365210, 365241, G11C 1300
Patent
active
048112984
ABSTRACT:
A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit. The output of the comparator circuit is directly connected to the input of a first driver circuit for the redundant word line, and furthermore to an OR circuit which is also controlled by a read/write control circuit, and which is connected to the decoder and to a clamp circuit that is directly connected to the input of a second word line driver circuit, and continuously maintains the potential following a deselect signal applied on that level, which requires a minimum of power.
REFERENCES:
patent: 3222653 (1965-12-01), Rice
patent: 3573758 (1971-04-01), Henle et al.
patent: 3665473 (1972-05-01), Heimbigner
patent: 3753235 (1973-08-01), Daughton et al.
patent: 3753244 (1973-08-01), Sumilas et al.
patent: 3755791 (1973-08-01), Arzubi
patent: 4251876 (1981-02-01), McKenny et al.
patent: 4592024 (1986-05-01), Sakai et al.
patent: 4737935 (1988-04-01), Wawersig et al.
IBM Tech. Disc. Bulletin, L. M. Terman, vol. 25, No. 4, Sep. '82, pp. 2135-2136.
IBM Tech. Disc. Bulletin, H. P. Schlaeppi, vol. 7, No. 9, Feb. '65, p. 808.
Helwig Klaus
Lohlein Wolfdieter
Tong Minh H.
Chadurjian Mark F.
Fears Terrell W.
International Business Machines - Corporation
Limanek Stephen J.
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