Redundant memory circuit

Details Redundant memory circuit Redundant memory circuit

1978-01-09

1981-02-10

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365210, 307238, G11C 1140

Patent

active

042505704

ABSTRACT:
A redundant memory circuit for a memory array in which the memory has a preselected number of rows and columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified addresses associated therewith and redundant decoders coupled thereto. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith.

REFERENCES:
patent: 3753244 (1973-08-01), Sumilas
patent: 4007452 (1977-02-01), Hoff

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