Integrated timer for power management and watchdog functions

Details Integrated timer for power management and watchdog functions Integrated timer for power management and watchdog functions

1996-01-24

1998-07-21

Sheikh, Ayaz R.

G06F 132

Patent

active

057846278

ABSTRACT:
A variety of clock intensive functions, such as interval timers, real-time clocks, and resettable timers for triggering watchdog reset and power management mode transitions, are provided using a single counter and timer event control logic. Such an integrated timer provides multiple time-based event signals from a single sequence of states. The integrated timer circuit includes sequential logic with a plurality of bit outputs, first and second configuration registers, and timer event control logic. The sequential logic supplies a sequence of states at the bit outputs in response to a clock signal. Variations of the sequential logic include a free-running binary counter, ripple counter, or gray code counter. State detection logic is coupled to the bit outputs of the sequential logic and coupled to the first and second configuration registers to receive first and second event descriptors. When the bit outputs of the sequential logic correspond to the first event descriptor, the state detection logic supplies a first state detection signal. When the bit outputs of the sequential logic correspond to the second event descriptor, the state detection logic supplies a second state detection signal. Masking logic selectively masks a first count of successive first state detection signals and supplies the first event signal in response to a subsequent one of the first state detection signals. The masking logic also selectively masks a second count of successive second state detection signals and supplies the second event signal in response to a subsequent one of the second state detection signals.

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