Dynamic random access memory device with staggered refresh

Details Dynamic random access memory device with staggered refresh Dynamic random access memory device with staggered refresh

1988-09-22

1990-03-27

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

36523006, 365227, G11C 700, G11C 800

Patent

active

049126784

ABSTRACT:
A dynamic random access memory (DRAM) comprises a divided plurality of memory array blocks. Each memory array block comprises a memory array having memory cells and a sense amplifier. In refresh operation, activating signals for activating each of the sense amplifiers are outputted. The output timings of the activating signals are different from each other, so that each of the sense amplifiers are activated at different timings. Consequently, a peak value of the current consumed by the activation of the sense amplifiers can be reduced.

REFERENCES:
patent: 4725987 (1988-02-01), Cates
patent: 4787067 (1988-11-01), Takemae et al.
patent: 4829484 (1989-05-01), Arimoto et al.

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