Memory cell array selection circuits

Details Memory cell array selection circuits Memory cell array selection circuits

1997-07-30

1998-07-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

36518901, 36523001, G11C 1300

Patent

active

057843279

ABSTRACT:
The invention enables random read and write operations into cells in an array of a memory device. It includes a decoding scheme wherein the memory chip has a row address bit which is used for the row decoding also participates (in some embodiments) in the column and bit-line decoding process.
The data is routed to and from the alongated bit-line by a selector at one bit-line end and/or by a separate selector at the other end of the same bit-line. This is accomplished by address circuitry and column selection circuitry. Data is read out and processed by a signal processing means such as a sense amplifier and/or data buffer.
In some embodiments such as flash EEPROM device, programming voltage VPP is applied to the bit-line only through the selector at one end of the bit-line.

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